Two-day Intel Xeon Phi workshop in Toronto

April 6, 2015 in Uncategorized

On May 19 and 20, 2015, Intel is giving a two-day workshop in Toronto for
software developers on the foundation needed for modernizing their code to take
advantage of parallel architectures found in both the Intel Xeon processor and
the Intel Xeon Phi co-processor.

The difference with the one-day workshop on the same topic given in Toronto on
October 27, is that the second day is a hands-on lab in which you get to use the
material and techniques presented in the first day.


The first day will cover:

  • Intel Xeon Phi architecture: purpose, organization, pre-requisites for good performance, future technology
  • Programming models: native, offload, heterogeneous clustering
  • Parallel frameworks: automatic vectorization, OpenMP, MPI
  • Optimization methods: general, scalar math, vectorization, multithreading, memory access, communication and special topics

The second day will cover:

  • Offload and Native: “Hello World” to complex; using MPI.
  • Performance Analysis: VTune.
  • Case Study: All aspects of tuning in the N-body calculation.
  • Optimization I: Strip mining for vectorization, parallel reduction.
  • Optimization II: Loop tiling, thread affinity.


Chestnut Residence & Conference Centre
St. Patrick’s Conference Room
89 Chestnut Street
Toronto, ON M5G 1R1


This is an external event organized by Intel. For registration please go to

Note that the first day is a prerequisite for the second.